Un método simple para pasar de un algoritmo a un modelo en VHDL - Muñoz, Gerardo (Ingeniería, 2001)
The following paper describes a methodology to convert an algorithmic model into a VHDL, without having to describe directly the hardware where the algorithmic runs. The solution is based to model the algorithmic with an Algorithmic State Machine (ASM) and furthermore model this ASM into a functional VHDL. During the development of this subject we are being introduce into VHDL.